Physical Design Engineer - Block Level, Subsystem Implementation

Etched

San Jose💼 Full-time🗓 2026-07-23 → 2026-09-25

Core

Own block-level and subsystem physical design end-to-end, driving PPA optimization for frontier AI inference clusters.

Role type

Senior IC physical design engineer (block-level/subsystem)

Builds

High-performance AI inference chips (frontier clusters)

Domain

Semiconductor hardware / AI infrastructure

Deliverable

production ML models

Required skills

Block-level physical design, timing closure, sign-off (DRC/LVS/IR drop/EM), RTL-to-GDSII flows, advanced process nodes (5nm+), scripting (Tcl/Python/Perl)

Preferred skills

ML/LLM architecture familiarity, Python programming, startup experience

Technologies

Cadence Innovus/Genus, Synopsys Fusion Compiler, PrimeTime, Tempus, Voltus, UPF

Responsibilities

Floorplanning, synthesis, placement, CTS, routing, STA debug, ECO implementation, 3rd party physical design supervision

Seniority

Senior, hands-on IC

Sourced via ashby · Listed on CareerPlan, which tracks 70,000+ jobs from 20+ sources.

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on **inference**. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.