SoC Static Timing Analysis (STA) Engineer, HBM
Core
Own chip-level timing sign-off and drive timing closure for next-generation HBM products across all modes and corners.
Role type
Senior IC Static Timing Analysis (STA) Engineer
Builds
Next-generation HBM memory chips and SoCs
Domain
Semiconductor / Advanced Node IC Design
Deliverable
production ML models | product features
Required skills
Chip-level STA ownership, Multi-mode multi-corner (MMMC) analysis, SDC constraint authoring, Python/Tcl scripting, Signal integrity analysis, Physical design collaboration, Tape-out sign-off experience
Preferred skills
HBM/DRAM design experience, Chiplet/3D IC design knowledge, DFT timing expertise
Technologies
Synopsys PrimeTime, Cadence Tempus, Python, Tcl
Responsibilities
Drive AI-hardware development for LLM workloads and AI-enabled timing closure methods; Own end-to-end STA and sign-off for clocks, resets, HBM interfaces, and DFT; Develop and validate hierarchical SDC constraints; Perform critical path analysis and ECOs for timing closure; Lead signal integrity and crosstalk analysis; Build STA automation flows for regression tracking and QoR dashboards; Conduct post-silicon timing correlation and define sign-off standards.
Seniority
Senior, hands-on IC
