Senior ASIC Physical Design Engineer, Netlisting
Core
Drive physical design of high-frequency, low-power CPUs, GPUs, and SoCs at block, cluster, and full-chip levels, focusing on netlist quality, equivalence checking, and timing closure.
Role type
Senior ASIC Physical Design Engineer (Netlisting)
Builds
High-performance CPUs, GPUs, and System-on-Chips (SoCs)
Domain
Semiconductor / ASIC Design
Deliverable
production ML models | product features
Required skills
Logic equivalence checking (FV), Clock-domain-crossing (CDC) checking, MTBF analysis, Logic synthesis, Static Timing Analysis (STA), Timing constraints management, EDA tool expertise, Scripting (Perl, TCL, Python)
Preferred skills
DFT timing closure, Workflow automation via AI
Technologies
Industry-standard EDA tools, Perl, TCL, Make, Python
Responsibilities
Drive physical design for CPUs/GPUs/SoCs; Perform equivalence checking and CDC/MTBF analysis; Manage timing convergence and ECO generation; Generate and manage timing constraints.
Seniority
Senior, hands-on IC