Digital Design RTL Engineer
Core
Design high-quality SystemVerilog RTL for advanced process nodes (5nm and below), focusing on PPA optimization, CDC/RDC analysis, and low-power design.
Role type
Senior IC RTL Design Engineer
Builds
SoC components including LPDDR5/6, DDR4/5, high-speed SerDes, and HBM protocols
Domain
Semiconductor / Digital Logic Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, RTL Design, PPA optimization, Clock Domain Crossing (CDC) analysis, Reset Domain Crossing (RDC) analysis, Low-power design techniques, SoC integration, High-speed SerDes, HBM protocols, LPDDR5/6, DDR4/5
Preferred skills
MSEE/PhD, 8+ years experience in SoC integration, LPDDR5/6, DDR4/5, high-speed SerDes, or HBM protocols
Technologies
SystemVerilog, 5nm process nodes
Responsibilities
Operate with autonomy taking designs from initial specification through to timing closure and physical design hand-off; Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule
Seniority
Senior, hands-on IC
