Senior DRAM RTL design engineer
Core
Design digital IP blocks for DRAM memory solutions from microarchitecture to RTL, covering full-chip integration, verification, and layout.
Role type
Senior IC RTL design engineer (DRAM)
Builds
High-performance DRAM memory chips (DDR5, LPDDR5, HBM)
Domain
Semiconductor / Memory / Digital Logic
Deliverable
production ML models | product features
Required skills
RTL design, asynchronous/synchronous design, CDC methodologies, SoC design flows (Lint, synthesis, STA, power analysis), CMOS circuit fundamentals, memory operation principles, floor-planning, placement, routing, functional/timing/power verification
Preferred skills
DRAM domain knowledge (DDR5, LPDDR5, HBM), AI/ML-assisted design flows, Spyglass experience, NAND memory design knowledge, SoC/ASIC semicustom flow experience
Technologies
Micron-specific simulators, industry standard EDA tools, Spyglass
Responsibilities
Define and review module interfaces and system-level architecture; drive full-chip integration including CDC, Lint, synthesis, STA and power analysis; oversee layout process including floor-planning, placement, and routing; perform block-level and full-chip verification; provide technical mentorship and participate in design reviews; drive innovation into future memory generations
Seniority
Senior, hands-on IC
