Senior RTL design engineer
Core
Design digital IP blocks from microarchitecture to RTL, drive full-chip integration, and oversee layout processes for memory and storage solutions.
Role type
Senior IC RTL design engineer (memory/SoC)
Builds
Digital IP blocks, full-chip designs, and memory storage products
Domain
Semiconductor, Memory (DRAM/NAND), SoC design
Deliverable
production ML models | product features
Required skills
RTL design, asynchronous/synchronous design, CDC methodologies, SoC design flows (Lint, synthesis, STA, power analysis), CMOS circuit design, memory operation fundamentals, floor-planning, placement, routing, functional/timing/power verification
Preferred skills
DRAM design (DDR5, LPDDR5, HBM), NAND memory design, SoC/ASIC semicustom flow, AI/ML-assisted design flows, Spyglass tool experience
Technologies
Micron-specific simulators, industry standard EDA tools, Spyglass
Responsibilities
Define and review module interfaces and system-level architecture; Accelerate RTL design optimization and design-space exploration using AI-based tools; Drive full-chip integration including CDC, Lint, synthesis, STA and power analysis; Oversee and manage the layout process including floor-planning, placement, and routing; Perform block-level and full-chip verification including functional, timing, power and reliability analysis; Provide technical mentorship and participate in design and methodology reviews
Seniority
Senior, hands-on IC
