DFT (Design For Test) Lead (6251)
Core
Lead the implementation and integration of advanced Design-for-Test (DFT) solutions across the silicon development lifecycle to ensure highly testable, manufacturable, and reliable ASIC designs.
Role type
Senior IC DFT Lead (ASIC)
Builds
Production-ready silicon devices with integrated DFT features and test architectures
Domain
Semiconductor / ASIC Design / Hardware Validation
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC DFT methodologies, scan architecture, memory BIST (MBIST), BISR, boundary scan, ATPG, EDA tools (Tessent, Xcelium, Genus, Tempus, PrimeTime), post-silicon debugging, JTAG protocols, RTL design integration
Preferred skills
DFT methodology standardization, team mentorship, system-level networking and photonic solutions understanding
Technologies
Tessent, Xcelium, Genus, Tempus, PrimeTime, JTAG, RTL
Responsibilities
Lead implementation of DFT features including scan, MBIST, BISR, and boundary scan; Develop innovative DFT IP and integrate testability into full-chip RTL; Perform post-silicon debugging and root cause analysis; Design and release ATPG patterns; Provide technical leadership and resolve complex DFT challenges
Seniority
Senior, hands-on IC with technical leadership
