Lead Design Engineer
Core
Implement, verify, and achieve timing closure for Palladium and Protium high-capacitive, high-performance hardware-assisted verification System-On-Chip (SOC) designs.
Role type
Senior IC physical design engineer (SoC verification)
Builds
Palladium and Protium SOCs for hardware-assisted verification
Domain
Semiconductor / Electronic Design Automation (EDA)
Required skills
RTL synthesis, floorplanning, clock tree synthesis, timing closure, IR drop analysis, physical verification, Linux server administration, Shell/Perl/TCL/Python scripting, knowledge of industry interfaces (PCI Express, DDR, LPDDR, SRAM, UCIe)
Preferred skills
Experience with 5nm, 3nm, and 2nm process nodes
Technologies
Innovus, Tempus, QRC, Voltus, Pegasus
Responsibilities
Work on RTL synthesis and floorplanning; Build clock trees and perform optimizations; Close timing, IR drop and physical verification; Review and Document designs for taping out; Interface with Front End RTL design teams and Back End Verification teams
Seniority
Senior, hands-on IC
