Principal Silicon Egineer
Core
Own STA execution methodology, drive timing closure, and manage signoff for full-chip designs.
Role type
Principal Silicon Engineer (Physical Design/STA)
Builds
Full-chip digital ICs with timing closure
Domain
Semiconductor physical design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
STA methodology development, timing budgeting, constraint development, ECO generation, tapeout signoff, flow automation, scripting (TCL/Perl), tool debugging, boundary timing analysis, full-chip bottleneck resolution
Preferred skills
None stated
Technologies
Synopsys DC, ICC2/Fusion-Compiler, PrimeTime, TSMC 5nm process
Responsibilities
Develop and update STA methodology, align flows with industry practices, resolve tool issues, define early-phase design planning including repeater planning and timing budgeting, drive STA milestones and rollups, manage ECO generation flows, ensure convergent STA process through tapeout, resolve boundary timing issues and full-chip bottlenecks, provide guidance for floorplan adjustments
Seniority
Principal, hands-on IC
