Principal Silicon Engineer
Core
Own full-chip/package integration, early-phase design planning, and drive convergence to tapeout signoff.
Role type
Principal silicon engineer (full-chip/package integration)
Builds
Integrated silicon chips and packages for system-level deployment
Domain
Semiconductor physical design and packaging
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
full-chip integration methodologies, C4/microbump development, RDL insertion & optimization, power domain management, floorplanning, tapeout signoff, vendor collaboration, flow automation, scripting (TCL/Perl), tool debugging
Preferred skills
expertise in power planning, chip/package interfaces, package signoff checklists, TSMC 5nm process experience
Technologies
DC, ICC2/Fusion-Compiler, PrimeTime, Calibre
Responsibilities
Define and drive integration milestones across project phases; manage interaction with package team and vendors; resolve power delivery and integration issues; provide guidance for floorplan adjustments; develop and maintain package signoff checklists; execute chip closure on schedule
Seniority
Principal, hands-on IC