Physical Design Engineer - Flow & Methodologies
Core
Architect and maintain automated RTL-to-GDSII physical design flows from first principles to enable rapid iteration and PPA gains for frontier AI inference clusters.
Role type
Senior IC Physical Design Methodology Engineer
Builds
Automated RTL-to-GDSII flows, CAD infrastructure, and reference flows for 3rd party services
Domain
Semiconductor hardware design (AI inference chips)
Deliverable
production ML models | infrastructure
Required skills
RTL-to-GDSII flow architecture, Tcl/Python automation, DRC-clean floorplanning, PPA tuning, timing correlation, EM/IR analysis, advanced process node design (5nm+), UPF low power methodology, EDA tool integration
Preferred skills
ML/LLM architecture familiarity, AI coding tools, compute farm optimization, startup experience
Technologies
Cadence Innovus/Genus, Synopsys Fusion Compiler, PrimeTime, Tempus, Voltus, Pegasus, Calibre
Responsibilities
Architect automated RTL-to-GDSII flows, build CAD infrastructure, drive PPA tuning, create PG mesh, establish timing correlation, define reference flows for 3rd party services, debug flow issues
Seniority
Senior, hands-on IC