Staff Engineer: STA Methodology & Sign-off Lead
Core
Architect and lead Static Timing Analysis (STA) methodology and sign-off architecture for large-scale System-on-Chip (SOC) designs to ensure timing convergence and eliminate bottlenecks.
Role type
Staff Engineer, VLSI STA Methodology & Sign-off Lead
Builds
Predictable, high-performance, and scalable paths to tape-out for edge-to-cloud AI hardware
Domain
Semiconductor design, VLSI, Advanced Process Nodes (7nm, 5nm)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
STA methodology, flow development, sign-off criteria, Multi-Mode Multi-Corner (MMMC), Hierarchical timing strategies, constraint (SDC) validation, advanced node timing phenomena, tool qualification, automation scripting (Tcl, Python, Perl), clock tree synthesis (CTS), floorplanning
Preferred skills
Cadence Tempus expertise, statistical margining (LVF/POCV), cross-functional leadership
Technologies
Cadence Tempus, Tcl, Python, Perl, SDC, CTS
Responsibilities
Define full-chip SOC timing sign-off criteria including MMMC definitions and derate strategies; Architect and maintain advanced STA and ECO flows; Evaluate and deploy new EDA tool features; Build scalable automation utilities for constraint management and timing audits; Partner with Physical Design to define CTS methodologies and floorplanning guidelines
Seniority
Senior Staff, hands-on IC with architectural scope
