Memory Design Engineer
Core
Design and validate ultra-low-power embedded SRAM and Register File IPs for advanced SoCs operating in sub-threshold and near-threshold voltage ranges.
Role type
Senior IC memory design engineer (embedded SRAM/RF)
Builds
Production-quality embedded memory IP for ultra-low-power SoCs
Domain
Semiconductor / Ultra-low-power SoC design
Deliverable
production ML models | product features
Required skills
SRAM architecture, SRAM compiler development, custom memory circuit design, timing and power characterization, silicon correlation, low-voltage failure analysis, Python/Tcl/Perl scripting
Preferred skills
Memory redundancy/repair algorithms, ECC, MBIST integration, 12nm FINFET technology experience
Technologies
Cadence Virtuoso, Spectre, HSPICE, Cadence Liberate MX
Responsibilities
Design ultra-low power embedded SRAM and Register File IPs; Develop and enhance SRAM compiler architectures; Design and optimize memory peripheral circuits; Optimize memory designs for Area, Performance, Leakage power, Dynamic power, yield and manufacturability; Analyze low-voltage failure mechanisms; Drive memory yield improvement through silicon debug and characterization; Develop automation scripts for compiler generation and characterization; Collaborate with architecture, physical design, timing, DFT/BIST, and foundry teams; Support memory IP integration into SoC products; Document design methodologies and silicon learnings
Seniority
Senior, hands-on IC
