Sr. Staff Physical Design Engineer
Core
Implement complex digital blocks for high-performance ASICs in advanced process nodes (3nm), driving timing closure, power integrity, and physical verification for photonics engines.
Role type
Senior Staff Physical Design Engineer (ASIC/Photonics)
Builds
3nm ASICs and photonics engines for AI data center infrastructure
Domain
Semiconductor manufacturing / AI Data Center Infrastructure
Deliverable
production ML models | product features
Required skills
Physical design flow (synthesis to verification), Timing closure (STA), Power analysis & optimization, Floor planning, DRC/LVS debugging, Scripting (TCL/Python/Shell), EDA tool integration
Preferred skills
3nm tape-out experience, Manual layout skills, Silicon photonics layout, EM/IR analysis, Cadence tools expertise
Technologies
3nm process nodes, Cadence EDA tools, STA tools, DRC/LVS tools, Python, TCL, Shell
Responsibilities
Implement digital blocks from synthesis through physical verification; Drive full-chip STA signoff and debug timing reports; Drive power analysis and optimization balancing area/performance; Execute full-chip floor planning, IO placement, and clock distribution; Debug and clean up DRC/LVS; Write automation scripts for flow customization
Seniority
Senior Staff, hands-on IC