R&D Engineer
Core
R&D Engineer responsible for physical design, place and route, timing closure, and tapeout integrity checks for top-level-route chips.
Role type
Senior IC physical design engineer (VLSI)
Builds
Integrated analog blocks and top-level-route chips
Domain
Semiconductor / VLSI physical design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Place and Route, CTS, DRC, LVS, Antenna, LUP, Calibre rule deck, Innovus, Perl scripting, TCL scripting, VLSI fabrication process, Timing ECOs, IR drop fixes, SPEF/GPD extraction, Signal EM fixes, Noise analysis
Preferred skills
STA, PTSI, timing analysis, Cadence tools expertise
Technologies
Cadence Innovus, Calibre
Responsibilities
Perform place and route, CTS, and routability analysis; Execute physical verification (DRC, LVS, Antenna, LUP); Integrate analog blocks and meet RC requirements; Implement timing ECOs, IR drop fixes, and signal EM fixes; Conduct integrity checks and manage post-tapeout release.
Seniority
Mid-Senior, hands-on IC
