Design Verification Technical Leader
Core
Lead verification of high-speed silicon photonics driver ICs (100/200/400G per Lambda) for Cisco's AI-era switching, routing, and wireless platforms.
Role type
Senior IC Design Verification Technical Leader
Builds
Hyper-scalable optical transceivers and modules (800G, 1.6T+) for next-gen data centers
Domain
Networking hardware / Silicon Photonics / ASIC Design Verification
Required skills
System Verilog, UVM, ASIC Design Verification, Python, Perl, TCL, Shell Scripts, SerDes IP, D2D PHY IP, ODSP, SoC verification, team leadership
Preferred skills
Formal Verification, Hardware Description Languages (Verilog/System Verilog), Emulation platforms (Veloce, HAPS), Design for testability, Debugging complex silicon issues
Technologies
System Verilog, UVM, Python, Perl, TCL, Shell Scripts, SerDes, ODSP, Veloce, HAPS
Responsibilities
Define and lead verification methodology and standards across multiple projects; Lead verification at block & chip level with high-speed IPs; Review specifications and influence architecture for testability; Mentor and coach verification engineers; Debug complex silicon and system-level issues; Support post-silicon bring-up and optimize integration
Seniority
Senior, hands-on IC with leadership responsibilities
