Design Verification Engineer - Power Management (Early Career or Experienced)
Core
Develop pre-silicon verification plans, environments, and test flows for mixed-signal designs to ensure bug-free silicon.
Role type
Design Verification Engineer (Mixed-Signal/Power Management)
Builds
Verification environments, test benches, and automated verification flows for RTL freeze and tape-out.
Domain
Semiconductor / Hardware Design Verification
Required skills
SystemVerilog, UVM, constrained random verification, test-bench development, simulation debugging, functional coverage analysis, hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), logic simulators
Preferred skills
Assertion Based Verification, Formal Verification (Formal Linting, Formal connectivity, user property verification), Python, Perl, TCL, Object Oriented Programming, mixed signal verification
Technologies
SystemVerilog, UVM, VHDL, Verilog, OVM, VVM, Python, Perl, TCL
Responsibilities
Develop verification plans in coordination with design leads and architects; Build and maintain verification test bench components and environments; Generate directed and constrained random tests; Run simulations and debug design and environment issues; Build functional coverage points, analyze coverage, and improve test environment to target coverage holes; Craft automated verification flows for block and chip level verification.
Seniority
Early Career or Experienced
