ASICS Design Verification Engineer
Core
Develop comprehensive pre-silicon test planning, testbenches, coverage, assertions, and formal verification for digital power IP within the complete verification lifecycle.
Role type
ASIC Design Verification Engineer
Builds
Digital power IP blocks and verification environments
Domain
Semiconductor / ASIC Design / Digital Verification
Required skills
SystemVerilog-UVM, Formal Verification, Perl/Python scripting, C/C++, RTL design concepts, AMBA Bus protocols
Preferred skills
Master's degree, Block-level testbench development, Assertion Based Formal Verification, VHDL
Technologies
SystemVerilog, UVM, Perl, Python, C, C++, Verilog, VHDL, AMBA (AXI/AHB/APB)
Responsibilities
Develop testbenches using SystemVerilog-UVM, Create coverage and assertion models, Implement formal verification properties, Develop automation for verification efficiency, Learn and deploy power-aware UPF verification flow
Seniority
Entry to Mid-level, Hands-on IC
