CPU IP Design & Verification Engineer – RISC-V (2027 New College Graduate)
Core
Design and verify advanced RISC-V processor IP, focusing on microarchitecture, RTL implementation, and functional verification.
Role type
CPU IP Design & Verification Engineer (New College Graduate)
Builds
RISC-V CPU IP cores for high-growth markets
Domain
Semiconductor / CPU Design / RISC-V
Required skills
SystemVerilog RTL design, CPU microarchitecture, functional verification, Python/C/C++ scripting, digital logic design, computer architecture
Preferred skills
RISC-V ISA knowledge, UVM/constrained-random verification, FPGA/ASIC project experience, Linux/Git, AI-assisted engineering tools
Technologies
SystemVerilog, Python, C/C++, RISC-V, UVM, Linux, Git
Responsibilities
Design RISC-V CPU microarchitecture and SystemVerilog RTL; Develop verification tests, assertions, and coverage; Run simulations and debug failures; Support power, performance, and area analysis; Automate design and verification workflows; Collaborate across architecture and verification teams
Seniority
Entry-level, New College Graduate
