ASIC Engineering Technical Leader
Core
Lead architecture and silicon debug of advanced Memory Built-In Self-Test (MBIST) solutions for complex SoCs.
Role type
Senior IC ASIC DFT Technical Lead (MBIST)
Builds
Memory test architecture, controllers, and custom diagnostic algorithms for SRAM, register files, ROMs, and embedded memories.
Domain
Semiconductor / ASIC Design / Memory Testing
Required skills
MBIST architecture, SRAM circuit design, memory architecture, soft/hard repair, custom test algorithms, Vmin debugging, post-silicon validation, yield improvement, failure analysis, RMA debug, Verilog/SystemVerilog, Python/Perl/Tcl scripting, IEEE 1149.1/1500/1687 standards
Preferred skills
Advanced process nodes (7nm/5nm/3nm), custom memory architectures, team leadership, silicon debug to production
Technologies
Verilog, SystemVerilog, Python, Perl, Tcl, IEEE 1149.1, IEEE 1500, IEEE 1687
Responsibilities
Develop and optimize MBIST and memory testing architecture; Lead hardware implementation of defined architecture; Develop and optimize MBIST controllers for various memory types; Define and implement standard and custom MBIST algorithms; Collaborate with memory compiler and IP teams; Lead tape out sign-off for MBIST deliverables; Debug Vmin-related memory failures; Lead post-silicon bring-up, memory diagnostics, and failure analysis; Drive yield improvement by analyzing manufacturing test data; Support customer-returned devices through RMA debug; Develop custom diagnostic algorithms; Lead technical reviews across cross-functional teams
Seniority
Senior, hands-on IC
