Senior Silicon DFT Micro Architecture Engineer, Google Cloud
Core
Develop DFT strategy and architecture for custom silicon solutions powering Google's data centers and computing infrastructure.
Role type
Senior IC DFT micro-architecture engineer
Builds
Custom silicon chips for Google Cloud infrastructure
Domain
Semiconductor hardware design and testing
Required skills
DFT design and verification, DFT specification and architecture, ASIC DFT synthesis, simulation and verification flow, DFT insertion, hierarchical DFT, high-speed I/O DFT, Analog DFT, Test Design Rule Checks (TDRC), DFT logic insertion, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, clock control block
Preferred skills
IP integration (memories, test controllers, TAP, Multi die SoCs), fault modeling, SoC cycles, silicon bringup, silicon debug
Technologies
ASIC, SoC, DFT tools
Responsibilities
Develop DFT strategy and architecture; Develop and drive die-level DFT validation strategy and execute TDRC fixes; Insert DFT logic and IP blocks; Document DFT architecture and test sequences; Generate and deliver production and debug patterns for post-silicon support
