Senior DFT Engineer
Core
Design-for-Test (DFT) architecture, verification, and post-silicon validation for complex semiconductor chips, focusing on test access mechanisms, BIST, and scan compression.
Role type
Senior DFT Engineer (Architecture & Methodology)
Builds
Next-generation DFX architectures, in-system-test architectures, and silicon debug workflows for automotive, industrial, and robotics safety platforms.
Domain
Semiconductor / VLSI / Hardware Design
Required skills
DFT architecture design, BIST (Memory/IO), Scan compression, ATPG, Fault modeling, Silicon debug & bring-up, Cross-functional collaboration (RTL, STA, Power), Mentorship
Preferred skills
Perl, Python, or Tcl scripting, ISO26262 functional safety knowledge
Technologies
ATE, Vendor verification tools, Perl, Python, Tcl
Responsibilities
Define and prototype next-generation DFX architectures; Develop and deploy DFT methodologies for new products; Collaborate with system architecture, ASIC design, and verification teams; Mentor junior engineers on test designs and trade-offs; Ensure system-level safety diagnostic test quality.
Seniority
Senior, hands-on IC
