DFT Engineer
Core
Implementation and verification of advanced DFT/DFD (Design for Test/Design for Debug) techniques for low power, multi-voltage designs to reduce test cost and increase product quality.
Role type
DFT Engineer
Builds
ASIC chips for communication and data processing
Domain
Semiconductor / Digital ASIC Design
Required skills
DFT/DFD techniques, scan, MBIST, fault models (Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, Cell Aware), JTAG, Scan Compression, ATPG, Fault Simulation, at-speed testing, EDA ATPG and insertion tools, DFT implementation, coverage analysis, gate-level simulation, pre-silicon and post-silicon debugging
Preferred skills
Low power design, multi-voltage domain design, core-based test methodology, scan isolation
Technologies
EDA ATPG tools, MBIST tools, JTAG, Scan Compression tools
Responsibilities
DFT pattern generation, coverage analysis, debug, running and debugging gate-level simulations, DFT implementation, Scan/ATPG, MBIST insertion/validation
Seniority
Mid-level, hands-on IC
