Principal Engineer - Ecosystem IP Quality
Core
Qualify and validate semiconductor IP libraries across technology platforms, ensuring compatibility with PDK updates and supporting customer tape-outs.
Role type
Principal Engineer, IP Quality & Validation
Builds
Qualified IP merge kits and validated IP deliverables for customer silicon production
Domain
Semiconductor manufacturing, IC design, Physical Verification
Required skills
System Verilog, Verification methodology, DFT/scan insertion/ATPG, Functional test vector generation, PHY co-simulation (RTL+Spice), Cadence co-sim environment, Digital circuit design for PHY protocols, Tetramax models, ATPG coverage, IC process knowledge, Layout design, Physical verification (DRC/LVS/DFM), Scripting & automation
Preferred skills
RF Design, Analog specific knowledge
Responsibilities
Perform incoming IP QA against checklists and issue certificates of approval/non-conformance, Qualify IP merge kits for tape-out, Define comprehensive test cases for IP qualification and regression, Assess IP impact based on PDK updates, Perform IP regression (Physical verification DRC/LVS/DFM, PEX extraction, Spice simulation), Consolidate and review IP assessment results, Chair stakeholder meetings to drive closure of IP issues, Support scripting and automation for efficiency, Document technical issues and assessment reports, Support customer queries regarding IP technical issues.
Seniority
Principal, hands-on IC design expert
