CPU IP Design & Verification Intern – RISC-V Processor Development (Summer 2027)
Core
Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development, including instruction fetch, decode, execution, caches, and memory interfaces.
Role type
Summer intern CPU IP design and verification engineer
Builds
RISC-V processor IP blocks for high-performance, power-efficient semiconductor solutions
Domain
Semiconductor / CPU Design / RISC-V Architecture
Required skills
SystemVerilog, Python, C/C++, digital logic design, computer architecture fundamentals, simulation and regression testing, debugging with waveforms and traces
Preferred skills
RISC-V ISA knowledge, UVM/constrained-random verification, FPGA/ASIC project experience, Linux/Git, assembly programming
Technologies
SystemVerilog, Python, C/C++, UVM, Linux, Git, FPGA, ASIC
Responsibilities
Support RTL design and development of CPU microarchitecture; Develop verification tests, assertions, and functional coverage; Run simulations and debug failures using logs and waveforms; Support power, performance, and area analysis; Develop automation scripts for design and verification productivity
Seniority
Intern
