Design Verification Engineering Intern
Core
Validate IP and subsystem-level designs for high-performance semiconductor products in consumer markets using System Verilog and simulation environments.
Role type
Design Verification Intern
Builds
Verification plans, testbench components, and simulation environments for digital IP blocks and subsystems.
Domain
Semiconductor / ASIC/SoC Design
Required skills
System Verilog, UVM, RTL design principles, digital logic design, computer architecture, scripting (Python/Perl/Tcl/Bash), simulation workflows
Preferred skills
EDA tools (Xcelium), SoC design concepts, Bus protocols (AXI, AHB, APB), Assertions (SVA), coverage-driven verification
Technologies
System Verilog, UVM, Xcelium, Python, Perl, Tcl, Bash
Responsibilities
Develop and execute verification plans for digital IP blocks and subsystems; Develop, enhance, and maintain testbench components; Run simulations, analyze results, identify failures, and help debug issues; Create directed and constrained-random tests; Perform functional, code, and assertion coverage reporting; Work closely with design and architecture teams to clarify specifications; Support automation flows and continuous regression infrastructure; Document verification environments, methodologies, and results
Seniority
Intern
