Design Verification Engineer
Core
Owns verification of custom IP blocks or subsystem integrations, developing strategies and test plans to ensure design quality.
Role type
Design Verification Engineer
Builds
Custom IP blocks and IP subsystems
Domain
Semiconductor hardware design and verification
Required skills
UVM, System Verilog, Python, random-stimulus generation, coverage-driven verification, formal verification, debugging, test plan development, IP verification lifecycle management
Preferred skills
Generative AI application, scripting, mentorship
Technologies
UVM, System Verilog, Python, AXI, CHI, PCIe, CXL, AMBA
Responsibilities
Develop UVM-based or Formal verification environments, run and debug simulations, apply coverage-based techniques to find bugs, mentor team members, define verification strategies and test plans
Seniority
Mid-level, hands-on IC
