Lead Engineer – IC Verification
Core
Lead IC Verification Engineer developing and maintaining SystemVerilog/UVM-based verification environments for complex digital RTL blocks in wireless modem baseband and PHY-layer subsystems.
Role type
Senior IC verification engineer (wireless modem/PHY)
Builds
Wireless SoCs for Wi-Fi and low-power IoT devices
Domain
Semiconductor / Wireless Communications / Digital Signal Processing
Required skills
SystemVerilog, UVM, constrained-random verification, functional coverage, C-based reference models, RTL debugging, mixed-signal verification, digital communication systems, PHY-layer concepts
Preferred skills
IEEE 802.11 Wi-Fi, 4G/5G cellular, OFDM, DSP blocks (FFT, FIR, correlators, FEC), subsystem-level verification, AI-powered tools
Technologies
SystemVerilog, UVM, C, Wi-Fi, 4G/5G, FFT, FIR, FEC
Responsibilities
Develop and maintain SystemVerilog/UVM-based verification environments; Design and implement module-level and subsystem-level testbenches; Define and execute comprehensive verification plans; Drive constrained-random verification and coverage closure; Perform bit-exact verification with C-based reference models; Debug complex RTL and testbench issues; Collaborate across functional teams to resolve integration challenges; Participate in design reviews and verification planning.
Seniority
Senior, hands-on IC
