Physical Verification Engineer
Core
Ensure ASIC and SoC designs are clean, correct, and ready for tapeout by running physical verification checks and debugging violations.
Role type
Physical Verification Engineer
Builds
ASIC and SoC designs ready for tapeout
Domain
Semiconductor / VLSI
Required skills
DRC, LVS, antenna, layout verification concepts, Calibre, ICV, Pegasus, Tcl, Perl, Python, shell scripting
Preferred skills
Advanced-node signoff, foundry rule decks, stream-out/OASIS or GDSII generation, PV automation, regression infrastructure
Responsibilities
Run and analyze physical verification checks (DRC, LVS, tapeout-quality signoff), Debug physical verification violations and partner with design teams, Review layout, netlist, and runset interactions to identify root causes, Support full-chip and block-level verification readiness, Improve physical verification flow quality, turnaround time, and automation, Collaborate with methodology, CAD, and foundry-facing teams on rule interpretation
Seniority
Mid-level, hands-on IC
