Mixed Signal IP Verification Engineer
Core
Functional verification of Mixed Signal Power Delivery IPs (Voltage Regulator, ADC, DAC) to ensure design meets specification.
Role type
Mixed Signal IP Verification Engineer
Builds
Mixed Signal Power Delivery IPs for Client SOCs
Domain
Semiconductor / Mixed Signal Analog & Mixed Signal (AMS)
Required skills
UVM, System Verilog, Mixed Signal IP verification, AMS simulation, RTL code interpretation, Behavioral Model (BMOD) code, validation plan implementation, schematic debugging
Preferred skills
Digital IP verification, technical communication, AI tools for automation
Technologies
UVM, System Verilog, EDA tools, AMS simulators
Responsibilities
Develop test plans and add stimuli/checkers for Mixed Signal IPs; Debug pre-silicon verification issues; Collaborate with RTL and Analog Design Engineers; Maintain verification infrastructure; Lead Mixed Signal Validation (MSV) activities.
Seniority
Mid-Senior, hands-on IC
