Senior ASIC Design Verification Engineer
Core
Define, design, and verify high-performance ASICs and subsystems for Cisco's data center switching, routing, and wireless products.
Role type
Senior IC ASIC Design Verification Engineer
Builds
Cluster and chip-level Design Verification (DV) environments and test plans for ASICs
Domain
Semiconductor hardware design and verification
Required skills
System Verilog, UVM methodology, OOP concepts, Perl scripting, Python scripting, constraint-random stimulus, directed stimulus, gate-level simulation, emulation environment support, RTL design qualification, block-level issue resolution, cluster and chip-level verification, functional coverage implementation
Preferred skills
Forwarding logic, parsers, P4, emulation platforms (Veloce, Palladium, Zebu, HAPS), formal verification tools (IEV, VC Formal), protocol knowledge (PCIe, CXL, Ethernet, RDMA, DDR, TCP)
Technologies
System Verilog, UVM, Perl, Python, Veloce, Palladium, Zebu, HAPS, IEV, VC Formal
Responsibilities
Define new verification methodologies and develop reusable code; lead design verification efforts and drive reviews; architect and maintain DV environment infrastructure; build DV environments from scratch; develop and enhance test plans using constraint-random and directed stimulus; ensure comprehensive verification coverage; qualify RTL designs via gate-level simulation; support design testing in emulation environments; debug issues at ASIC, SW, and Systems levels
Seniority
Senior, hands-on IC
