ASIC DFT Engineering Technical Leader
Core
Lead Design-for-Test (DFT) strategy and implementation for next-generation networking ASICs, collaborating with RTL and physical design teams to drive quality from early design through post-silicon validation.
Role type
Senior IC ASIC DFT Technical Leader
Builds
High-performance networking chips (Switching, Routing, Wireless)
Domain
Semiconductor / Hardware / Networking
Required skills
ATPG, EDA tools (TestMax, Tetramax, Tessent), Gate-level simulation, VCS debugging, Post-silicon validation, Scan insertion
Preferred skills
Verilog (custom DFT logic), JTAG protocols (p1500, p1687), SSN, Scripting (Tcl, Python/Perl), Static timing analysis
Technologies
VCS, TestMax, Tetramax, Tessent, Tcl, Python, Perl
Responsibilities
Collaborate with Front-end RTL and backend physical design teams to define DFT requirements early; Lead DFT and quality processes through Implementation flow and post-silicon validation; Work with ATE engineers on pattern translation and validation; Drive scan insertion and timing closure activities.
Seniority
Senior, hands-on IC
