Senior/Staff Verification Engineer
Core
Drive functional verification of complex digital ICs for automotive and industrial applications from requirements analysis to coverage-driven sign-off.
Role type
Senior/Staff IC verification engineer
Builds
Reusable SystemVerilog/UVM verification environments, agents, sequences, scoreboards, and coverage solutions
Domain
Semiconductor / Digital IC design
Required skills
SystemVerilog, UVM, constrained-random verification, coverage-driven verification, verification planning, regression management, digital design fundamentals, SVA, formal verification
Preferred skills
Mentoring junior engineers, automation initiatives, continuous improvement efforts
Technologies
SystemVerilog, UVM, SVA
Responsibilities
Analyze product requirements and architectures to define verification strategies and acceptance criteria; Create and maintain verification plans with clear requirements traceability; Develop and enhance reusable verification environments including agents, sequences, and scoreboards; Design and execute constrained-random, directed, error-injection, and formal verification test scenarios; Drive regressions, debug verification and design issues, and ensure timely defect closure; Measure, analyze, and close functional, code, and assertion coverage gaps to achieve sign-off goals; Contribute to system-level verification, technical reviews, and mentoring of junior engineers.
