ASIC Verification Engineering
1,761 open positions
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Senior ASIC Verification Engineer IntelIsrael, Haifa 3mo Senior verification engineer owning verification strategy and execution for complex AI acceleration IPs and subsystems, building environments to sign-off.
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CAD Engineer – PDV AppleHaifa, Israel 3mo Architect, develop, and maintain physical design verification (PDV) flows for high-performance, power-efficient silicon chips.
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Zebu flow Engineer SiFiveBengaluru, Karnataka, India 3mo Build and maintain modular flows for modeling RISC-V CPUs on Synopsys Zebu emulators and FPGA platforms, supporting root cause analysis and debug workflows.
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Senior ASIC Verification Engineer NVIDIAUS, NC, Durham $136k3mo Verify design, architecture, and micro-architecture of high-performance SoCs and GPUs, specifically focusing on memory subsystem units.
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<GPU>GPU Design Verification Lead MediaTekHsinChu 3mo Lead GPU verification efforts across unit, subsystem, and full-chip levels, defining strategy and driving closure for graphics and compute features.
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Senior Design Verification Engineer ON SemiconductorBangalore, Karnataka, India 3mo Develop IP for next generation Automotive, Industrial & Medical products, including complex mix-signal IPs and analog blocks like DACs, ADCs, PLL, and wireless interfaces.
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Sensors Design Verification Engineer, Senior - Cork, Ireland↗ QualcommCork, County Cork, Ireland 3mo Senior IC verification engineer developing testbenches and verification environments for sensor algorithms RTL to ensure ASIC tapeout quality.
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Digital Design Verification Engineer Advanced Micro Devices, IncMARKHAM, Canada 3mo Develop and enhance System Verilog/UVM-based testbenches to verify new and existing PCIe features for AMD's high-performance computing and AI processors.
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Staff Design Verification Engineer, AI HW TenstorrentSanta Clara $100k3mo Validating custom AI compute cores, RISC-V CPUs, and chiplet-based architectures for datacenter, edge, and automotive AI.
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Field Application Engineer Siemens-EdaBangalore, IND, India 3mo Senior Application Engineer providing technical selling, support, and evaluation of Siemens EDA's Design and Verification portfolio to chip, board, and system design customers.
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Engineer /Senior Engineer (Verification) ArmBengaluru, India 3mo Integrate Arm CPU and system IPs into full reference platforms and perform stress verification across simulation and emulation environments.
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Principal Digital Engineer Renesas-ElectronicsAustin, TEXAS, us 3mo Define scalable verification and validation methodologies for advanced digital power management products used in AI, datacenter, and high-performance computing applications.
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Senior Verification Engineer MicrosoftUnited States, California, Mountain View 3mo Lead pre-silicon verification for custom IP and subsystem components in AI SoCs, ensuring architectural and micro-architectural intent is met.
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Sr Physical Design Engineer AnalogdevicesIndia, Bangalore, RMZ 3mo Own and drive full-chip and block-level physical verification (PV) signoff activities, including DRC, LVS, PEX, and EM/IR drop analysis for analog, digital, and mixed-signal designs.
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ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years CiscoBangalore, India 3mo Lead Design-for-Test (DFT) implementation for complex ASICs in Cisco's Silicon One architecture, ensuring testability and debug capabilities for switching, routing, and wireless hardware.
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Staff Engineer - ASIC SOC Verification MicronHyderabad, Telangana, India 3mo Create SoC verification plans and develop SV/UVM-based testcases, monitors, and flows for ASIC verification including test controller, MBIST, and functional vectors.
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Design Verification Engineer AlteraRegus, Madhapur 3mo Develops, validates, and debugs software abstractions and frameworks for FPGA acceleration to support embedded, data center, and communication clients.
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Staff/ Principal Design Verification Engineer AsteralabsTel Aviv 3mo Develop ASIC verification environments and testbenches to validate high-performance digital blocks, subsystems, and full-chip designs for next-generation AI connectivity silicon.
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AMS Verification Engineer (all gender) AltenRemote 3mo AMS verification of I/O interfaces, defining verification strategies, developing testbenches, executing simulations, and debugging functional, electrical, and timing issues.
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Sr Principal Design Engineer CadenceSAN JOSE $154k3mo Senior Solutions Engineer developing hardware emulation and FPGA prototyping platforms for semiconductor customers, bridging R&D and customer needs to solve complex high-speed protocol challenges.
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ASIC Verification Engineer BroadcomUSA-CA Irvine Alton Parkway Bldg 2 $101k3mo Develop verification environments and testbench components for high-speed interconnect ASICs (100Gbps to 400Gbps) using SystemVerilog UVM, collaborating with architecture and firmware teams.
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FPGA Engineer Sapsol-Technologies-IncMelbourne, Florida, United States 3mo Develop RTL designs, verification environments, and hardware lifecycle management for FPGA/ASIC products.
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Principal Modem PHY IP Design Verification Engineer - Terawave BlueoriginCentral Texas, US $269k3mo Lead verification of advanced modem PHY IP for next-generation wireless ASIC platforms within the Terawave satellite communications network.
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