Distinguished Formal Verification
Core
Define and evolve formal verification strategy, methodologies, and best practices for next-generation connectivity products (PCIe, CXL, Ethernet, UCIe, UALink) to ensure design correctness and catch critical corner-case bugs.
Role type
Distinguished Engineer, Formal Verification (Strategy & Technical Authority)
Builds
Rack-scale AI infrastructure connectivity solutions
Domain
Semiconductor hardware design verification / High-speed serial protocols
Deliverable
production ML models | product features
Required skills
Formal verification strategy definition, SystemVerilog/Verilog, Python/Perl scripting, assertion-based model checking, complexity reduction techniques, cross-functional technical leadership, design review participation
Preferred skills
Synopsys VCFormal, Cadence JasperGold, static proof verification, CI/CD automation, high-speed serial protocol expertise (PCIe Gen 6/7, CXL, Ethernet, UCIe, UALink), industry standards body participation, patent/publication record, distributed team mentoring
Technologies
Synopsys VCFormal, Cadence JasperGold, SystemVerilog, Verilog, Python, Perl
Responsibilities
Define formal verification strategy and methodologies; Serve as technical authority on verification; Represent company in industry forums and standards bodies; Develop formal verification test plans and models; Mentor global engineering teams; Collaborate with design teams on RTL verification and PPA optimization
Seniority
Distinguished, Strategy & Mentorship
