Senior Memory Circuit Design Verification Engineer
Core
Senior IC verification engineer driving full-chip gate-level verification for advanced memory technologies (DDR5/6, LPDDR5/6) operating at high speeds.
Role type
Senior IC verification engineer (memory circuit design)
Builds
Full-chip gate-level custom designs for DDR5, LPDDR5, DDR6, and LPDDR6 memory products
Domain
Semiconductor / Memory / Digital Logic
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, gate-level simulation with delays, timing analysis (setup/hold), DRAM/SRAM architecture knowledge, AI-assisted verification tooling
Preferred skills
Experience with PLI coding, multi-functional task execution, cross-functional collaboration on new verification flows
Technologies
Verilog, SystemVerilog, UVM, simulation tools, AI-assisted verification tools
Responsibilities
Guide verification effort direction; simulate, analyze, and debug pre-silicon full-chip designs; develop test cases/stimulus for functional coverage; develop verification methodology and environments; co-work on new verification flows; maintain test benches/vectors and run regressions; identify pain points for AI-based automation
Seniority
Senior, hands-on IC
