Senior ASIC Verification Engineer
Core
Senior verification engineer owning verification strategy and execution for complex AI acceleration IPs and subsystems, building environments to sign-off.
Role type
Senior IC ASIC verification engineer (AI hardware)
Builds
Verification environments and plans for AI acceleration IPs and subsystems
Domain
Semiconductor / AI Hardware
Deliverable
production ML models
Required skills
SystemVerilog, UVM, constrained-random verification, coverage-driven verification, verification planning, technical leadership, mentorship
Preferred skills
AI tool integration in verification flow, experience with accelerators/datapath/compute-heavy IPs, familiarity with DFT and bring-up
Technologies
SystemVerilog, UVM
Responsibilities
Own verification strategy and execution for complex AI IPs; Build verification environments and drive coverage closure; Provide technical leadership and mentorship; Champion AI tools in the verification flow; Collaborate with architects, designers, DFT, and emulation teams
Seniority
Senior, hands-on IC with broad technical influence
