Zebu flow Engineer
Core
Build and maintain modular flows for modeling RISC-V CPUs on Synopsys Zebu emulators and FPGA platforms, supporting root cause analysis and debug workflows.
Role type
System Validation Engineer (RISC-V / Emulation)
Builds
RISC-V CPU models on Synopsys Zebu and FPGA-based validation platforms
Domain
Semiconductor / Chip Design / RISC-V Architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Logic design, Verilog, FPGA porting, Linux, Python scripting, BASH, Root cause analysis, Debug workflows, Waveform dumping, ILA/JTAG debugging
Preferred skills
RISC-V software ecosystem knowledge, SiFive internal build system experience
Technologies
Synopsys Zebu, Verilog, Python, BASH, Linux, FPGA, ILA, JTAG
Responsibilities
Build and maintain modular flows for Synopsys Zebu models; Execute root cause and failure analysis across RISC-V CPU hardware and software; Facilitate debug using ZeBu features, waveform dumping, ILA, and JTAG; Develop failure hypotheses through systematic elimination; Create and support Python-based scripts to automate debug workflows; Work cross-functionally with software and validation engineering departments.
Seniority
Entry-level to Mid-level, hands-on IC
