Design Verification Engineer
Core
Develops, validates, and debugs software abstractions and frameworks for FPGA acceleration to support embedded, data center, and communication clients.
Role type
Design Verification Engineer (FPGA/ASIC)
Builds
Verification environments, testbenches, and validation frameworks for hardware IP
Domain
Semiconductor / FPGA / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (verification environments)
Required skills
SystemVerilog, UVM, Verilog, VHDL, Python, Perl, Tcl, SVA, formal verification, coverage-driven verification, assertion-based verification
Preferred skills
AMBA protocols (AXI, ACE, CHI, APB), PCIe, Ethernet, simulation and debug tools
Technologies
SystemVerilog, UVM, Python, Perl, Tcl, SVA
Responsibilities
Collaborate with architects to define verification strategies and test plans; Develop constrained-random verification environments; Create directed and random test cases; Develop verification components (drivers, monitors, scoreboards, checkers); Execute simulation regressions and debug failures; Define and track coverage metrics; Develop automation scripts for verification flows.
Seniority
Mid-level, hands-on IC
