Silicon Verification Engineer
Core
Develop and verify high-performance DDR PHY intellectual property for cutting-edge SoCs in data center, mobile, and automotive markets.
Role type
Entry-level silicon verification engineer
Builds
DDR PHY IP for high-performance SoCs
Domain
Semiconductor / Memory Interface / Digital Design
Required skills
SystemVerilog, UVM, digital design fundamentals, simulation tools (VCS/Xcelium/Questa), Python/Perl/TCL scripting, functional coverage modeling
Preferred skills
DDR memory protocols, PHY architecture, analog design basics
Technologies
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Mentor Questa, Python, Perl, TCL
Responsibilities
Develop UVM-based verification environments, write and execute test plans and constrained-random tests, debug simulation failures and analyze waveforms, create verification collateral (testbenches, checkers, scoreboards), perform regression runs and track functional coverage, contribute to automation scripts
Seniority
Entry-level, hands-on IC
