ASIC DFT Engineering Technical Leader | ATPG, MBIST, SSN, SCAN | 12+ years
Core
Lead Design-for-Test (DFT) implementation for complex ASICs in Cisco's Silicon One architecture, ensuring testability and debug capabilities for switching, routing, and wireless hardware.
Role type
Senior IC ASIC DFT Technical Leader
Builds
Production ASICs for enterprise and service provider networking switches and routers
Domain
Semiconductor hardware design / Networking infrastructure
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
DFT architecture (ATPG, MBIST, SSN, SCAN), JTAG protocols, EDA toolsets (TestMax, Tetramax, Tessent, PrimeTime), System Verilog, Gate-level simulation, ATE pattern development, Tcl/Python/Perl scripting
Preferred skills
Custom DFT IP development, DFT CAD infrastructure, Test Static Timing Analysis, Post-silicon validation using DFT patterns
Technologies
VCS, TestMax, Tetramax, Tessent, PrimeTime, Tcl, Python, Perl
Responsibilities
Drive DFT requirements early in the design cycle with RTL and physical design teams; Implement DFT features supporting ATE, in-system test, and diagnostics; Develop innovative DFT IP and coordinate full-chip integration; Lead DFT and quality processes through implementation and post-silicon validation; Craft debug solutions with minimal mentorship
Seniority
Senior, hands-on IC
