Principal Modem PHY IP Design Verification Engineer - Terawave
Core
Lead verification of advanced modem PHY IP for next-generation wireless ASIC platforms within the Terawave satellite communications network.
Role type
Principal Modem PHY IP Design Verification Engineer
Builds
Scalable verification environments, testbenches, and coverage models for modem PHY subsystems.
Domain
Space communications, satellite networks, wireless ASICs, modem PHY, DSP systems.
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, digital design verification, ASIC/SoC verification, modem/baseband verification, DSP systems knowledge, Python/Perl/shell scripting, debugging RTL/testbench/model correlation.
Preferred skills
mmWave/sub-THz/Terahertz systems, satellite/space communications, 5G/6G systems, high-throughput wireless backhaul, MATLAB/C/C++ reference models, formal verification, emulation/FPGA prototyping, RF/system impairments knowledge.
Technologies
SystemVerilog, UVM, Python, Perl, shell, MATLAB, C/C++, FPGA, emulation tools.
Responsibilities
Develop and execute verification strategies for modem PHY IP; build block-level and subsystem-level verification environments; create testbenches, stimulus, checkers, scoreboards, and coverage models; verify PHY functions including modulation/demodulation, synchronization, channel estimation, MIMO/beamforming, and FEC; correlate RTL behavior against reference models; define and track coverage metrics; debug design and integration issues; support FPGA prototyping and post-silicon debug; contribute to regression automation and CI flows.
Seniority
Principal, hands-on IC with strategy & mentorship
