ASIC Verification Engineer
Core
Develop verification environments and testbench components for high-speed interconnect ASICs (100Gbps to 400Gbps) using SystemVerilog UVM, collaborating with architecture and firmware teams.
Role type
ASIC Verification Engineer
Builds
Physical layer transceivers (PHYs) for AI data centers, enterprise networks, and server virtualization
Domain
Semiconductor / High-Speed Interconnects
Deliverable
production ML models | product features
Required skills
SystemVerilog UVM, IEEE Ethernet protocols, chip architecture understanding, Verilog/VHDL, C/C++ programming, Python/TCL scripting
Preferred skills
Object Oriented Programming, infrastructure automation scripting
Responsibilities
Develop advanced verification environment and testbench components, participate in block level and chip level verification tasks, develop scripts and tools for efficiency and quality improvements
Seniority
Mid-level IC Engineer
