Staff/ Principal Design Verification Engineer
Core
Develop ASIC verification environments and testbenches to validate high-performance digital blocks, subsystems, and full-chip designs for next-generation AI connectivity silicon.
Role type
Staff/Principal Design Verification Engineer (ASIC)
Builds
Verification environments for AI infrastructure connectivity chips
Domain
Semiconductor / AI Infrastructure / Connectivity
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, functional verification, coverage modeling, debugging, assertion-based verification, constrained-random testing
Preferred skills
Formal verification, emulation flows, Python/Tcl scripting, AMBA/PCIe/Ethernet/CXL protocols, connectivity silicon verification
Technologies
SystemVerilog, UVM, Python, Tcl
Responsibilities
Develop and maintain SystemVerilog/UVM components including traffic generators, monitors, and checkers; Implement functional coverage models and analyze results; Debug complex hardware bugs in collaboration with design engineers; Drive designs toward 100% verification closure
Seniority
Staff/Principal, hands-on IC
