Staff DFT Engineer
Core
Design and implement Design-for-Test (DFT) architectures and strategies for next-generation AI connectivity chips to ensure silicon reliability and testability.
Role type
Staff DFT Engineer (Semiconductor)
Builds
Custom connectivity solutions for rack-scale AI infrastructure
Domain
Semiconductor / AI Infrastructure / High-speed interfaces
Deliverable
production ML models
Required skills
DFT architecture definition, JTAG/iJTAG, MBIST, Scan, ATPG, Static Timing Analysis (STA), gate-level simulation, EDA tool proficiency (Synopsys TestMAX, Mentor Tessent), scripting (Tcl, Perl, Python, Shell), logic design, verification, debug
Preferred skills
High-speed interface protocols (PCIe, Ethernet, CXL, UALink), chip bring-up, mass production activities, advanced process technologies (7nm and below)
Technologies
Synopsys TestMAX, Mentor Tessent, Tcl, Perl, Python, Shell, JTAG, MBIST, Scan, ATPG
Responsibilities
Own DFT journey from high-level architecture to backend implementation and post-production support; Develop comprehensive DFT strategies for next-generation connectivity platforms; Generate and optimize high-quality test and debug patterns; Perform Static Timing Analysis (STA) for DFT modes and conduct gate-level simulations; Collaborate with Architecture, Verification, and Backend teams; Automate and improve DFT implementation flows
Seniority
Staff, hands-on IC with strategic ownership
