ASIC DFT DV Technical Lead
Core
Lead Design-for-Test (DFT) and Design Verification (DV) for Cisco's silicon architecture, ensuring high-quality test plans and benches for ATE screening, in-system test, and debug.
Role type
Senior IC ASIC DFT/DV Technical Lead
Builds
Silicon devices (bare die & stacked die) for core Switching, Routing, and Wireless products (via careerplan.io/jobs/2019403-1-asic-dft-dv-technical-lead-at-cisco)
Domain
Networking hardware / Semiconductor / ASIC Design
Required skills
DFT verification, test planning, System Verilog, DVE/Verdi debugging, Tcl scripting, Python scripting, Perl scripting
Preferred skills
UVM, advanced System Verilog, JTAG protocol, scan architecture, MBIST, boundary scan
Technologies
System Verilog, DVE/Verdi, Tcl, Python, Perl, UVM
Responsibilities
Develop detailed test plans and test benches for DFT verification; Collaborate with RTL, physical design, and verification teams to integrate test logic; Drive innovative hardware DFT & test strategy for new silicon models; Mentor and guide DFT DV engineers
Seniority
Senior, hands-on IC with technical leadership
