Senior Design Verification Engineer
Core
Developing verification environments and testbenches to validate high-performance digital blocks, subsystems, and full-chip designs for next-generation AI connectivity silicon.
Role type
Senior IC design verification engineer (ASIC/UVM)
Builds
Functional verification environments for AI infrastructure connectivity chips
Domain
Semiconductor / AI Infrastructure / High-speed Interconnects
Deliverable
production ML models | product features
Required skills
SystemVerilog, UVM, functional verification, coverage modeling, debugging, testbench development, assertion-based verification, constrained-random testing
Preferred skills
Formal verification, emulation flows, Python/Tcl scripting, AMBA/PCIe/Ethernet/CXL protocols, connectivity silicon verification
Technologies
SystemVerilog, UVM, Python, Tcl, CXL, PCIe, Ethernet, NVLink, AMBA
Responsibilities
Develop and maintain SystemVerilog/UVM components including traffic generators, monitors, and checkers; Implement functional coverage models and analyze results; Debug complex hardware bugs in collaboration with design engineers; Drive designs toward 100% verification closure
Seniority
Senior, hands-on IC
