Staff Verification Engineer
Core
Developing and maintaining UVM-based verification environments, writing testbenches, and debugging RTL issues for complex IP and SoC designs.
Role type
Senior Hardware Verification Engineer (UVM)
Builds
Complex IP and System-on-Chip (SoC) designs
Domain
Semiconductor hardware verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM methodology, constrained-random verification, Formal Verification, Computer Architecture, Verilog/SystemVerilog, RTL Design, verification flows and tools, regression management, scripting (Python/Perl/Tcl)
Preferred skills
Semiconductor product development for automotive, industrial, or embedded systems
Technologies
UVM, Verilog, SystemVerilog, Python, Perl, Tcl, simulators, waveform viewers, coverage tools
Responsibilities
Develop and maintain UVM-based verification environments, write testbenches and test cases, analyze specifications and define verification plans, debug RTL issues, run regressions and monitor coverage metrics, perform root-cause analysis of failures
Seniority
Senior, hands-on IC
