Staff Design Verification Engineer, AI HW
Core
Validating custom AI compute cores, RISC-V CPUs, and chiplet-based architectures for datacenter, edge, and automotive AI.
Role type
Staff Design Verification Engineer (AI Hardware)
Builds
Scalable DV infrastructure, reusable verification environments, agents, and scoreboards for Tensix IP and subsystems.
Domain
Semiconductor / AI Hardware / RISC-V / Chiplet Architecture
Deliverable
production ML models | product features
Required skills
SystemVerilog, coverage-driven verification, constrained-random testing, Linux scripting (Python/Bash), RTL debugging, microarchitecture reasoning
Preferred skills
Functional safety (FuSa) verification, formal verification, SVA, formal property verification
Technologies
SystemVerilog, Python, Bash, CI/CD, EDA tools
Responsibilities
Own coverage goals and drive them to closure for Tensix IP; Build and maintain reusable verification environments and infrastructure; Develop constrained-random and directed tests; Debug complex issues across RTL and testbench; Evolve DV infrastructure including regression flows and CI/CD integration
Seniority
Staff, hands-on IC with strategic infrastructure ownership
