Senior/ Staff Formal Verification Engineer
Core
Define and execute formal verification strategy for complex semiconductor chips enabling AI scale-up and scale-out connectivity.
Role type
Senior/Staff Formal Verification Engineer (Semiconductor R&D)
Builds
Custom connectivity solutions and standards-based chip architectures for hyperscalers
Domain
Semiconductor hardware design, AI infrastructure, high-speed serial interfaces
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Formal verification methodologies, RTL design analysis, Jasper/VC Formal tools, SystemVerilog, UVM, corner-case bug detection, generic property architecture
Preferred skills
Full lifecycle ownership of complex blocks, high-speed serial interface verification, networking standards (Ethernet, NVLink, PCIe, UALink)
Responsibilities
Own and develop formal verification environments from scratch to sign-off; Apply formal verification strategies to prove design correctness; Collaborate with Architecture and Design teams to identify verification needs; Analyze verification results and resolve design issues; Architect reusable formal functions and properties across projects
Seniority
Senior/Staff, hands-on IC with strategic ownership
